A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

In-memory computing using emerging technologies such as resistive random-access memory (ReRAM) addresses the ‘von Neumann bottleneck’ and strengthens present research impetus to overcome wall. While many methods have been recently proposed implement Boolean logic in memory, latency of arithmetic circuits (adders consequently multipliers) implemented a sequence operations increases greatly with bit-width. Existing in-memory multipliers require $O(n^{2})$ cycles which is inefficient both terms energy. In this work, we tackle exorbitant by adopting Wallace Tree multiplier architecture optimizing addition operation each phase Tree. Majority primitive was used for since it better than NAND/NOR/IMPLY primitives. Furthermore, high degree gate-level parallelism employed at array level executing multiple majority gates columns array. manner, an notation="LaTeX">$O(n.log(n))$ achieved outperforms all reported multipliers. can be regular transistor-accessed without any major modifications its peripheral circuitry also energy-efficient.